This application claims the benefit of Korean Application No. 2000-27026, filed May 19, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to memory devices, and more particularly, to memory modules and computer system boards for use therewith.
As the performance of microprocessors (CPUs) has increased, current memory systems have generally been required to process increasingly large amounts of data at increasingly higher speed. This increased demand generally arises from elongation of word length, increases in clock frequency, and enlargement of data bus width. In particular, an increase in the width of an external data bus may require a corresponding increase in the storage capacity and data transmission speed of a memory system interconnected with the CPU. The transmission speed of the memory system, which indicates the amount of input and output data being transmitted per unit time, may be referred to as its bandwidth. A memory system having a wide bandwidth often uses a wide data bus that operates at a high frequency.
As the width of the data bus of a memory system increases, the size of memory modules used in such a system typically increases. The increase in the size of a memory module may arise from an increase in the number of memory chips used in the module and/or from an increase in the number of memory module pins.
FIG. 1 illustrates a conventional memory module having a loop-through structure. Referring to FIG. 1, a memory module 15 is mounted on a system board 10, and a plurality of memory chips 11, 12, 13, and 14 are mounted on the memory module 15. The memory chips 11, 12, 13, and 14 share a bus line (several such bus lines are typically present) and receive or send data which is input or output through module pins 16 and 17 and the bus line. The system board 10 has a terminating voltage terminal Vterm and a terminating resistor Rterm located between the terminating voltage terminal Vterm and the memory module pins 16 and 17. The terminating resistor Rterm is used in terminating the bus line.
In the conventional memory module 15, the bus lines of the memory chips 11, 12, 13, and 14 are connected to the terminating resistor Rterm through the memory module pins because the terminating resistor Rterm is built into the system board 10. Therefore, as the number of bus lines of the memory chips 11, 12, 13, and 14 increases, the number of memory module pins connected to the bus lines also increases. This generally increases the size of the memory module. The memory module pins are connected to a connector socket 18, which may introduce noise to data signals passing through the socket 18. As the number of contact points of the socket 18 through which bus lines pass increases, the performance of the bus lines may be degraded.
FIG. 2 is a diagram briefly illustrating a conventional system board 20. The system board 20 includes a plurality of memory modules 22, 23 that are connected to a memory controller 21 through a bus line IO BUS. A terminating resistor Rterm is installed between the bus line IO BUS and a terminating voltage terminal Vterm. The memory modules 22 and 23 are daisy chain connected to the bus line IO BUS of the memory controller 21. In this system board 20, a first memory module 22 adjacent to the memory controller 21 may have a smaller data propagation time than that of a second memory module 23 relatively far away from the memory controller 21. The operating speed of such a memory system is generally determined by the longest data propagation time.
In embodiments of the present invention, a memory module for use with a computer system board includes at least one memory chip connected to a bus line conductor and a terminating resistor connected to the bus line conductor. The memory module further includes a connector configured to connect the bus line conductor to bus line of the computer system board.
In other embodiments of the invention, a computer system board includes a bus line including a first branch configured to connect to a first memory module and a second branch configured to connect to a second memory module. The computer system board further includes a memory controller coupled to the first and second branches of the bus line at a single pin thereof. Each of the first and second memory modules may include a plurality of memory chips connected in common to a bus line conductor, a terminating resistor connected to the bus line conductor, and a connector that couples the bus line conductor of the memory module to a respective one of the first and second branches of the bus line of the computer system board.
In still other embodiments of the present invention, a computer system board includes a bus line including first and second branches. The computer system board includes a first switch that is operative to selectively couple a first plurality of memory modules to the first branch of a bus line of the system board. The computer system board further includes a second switch that is operative to selectively couple a second plurality of memory modules to the second branch of the bus line. The system board further includes a memory controller connected to the first and second branches of the bus line at a single pin thereof.